Design and Performance Analysis of 4-input Multiplexer Tree using FGMOS
The work proposed in this paper presents the design of Ultra Lowpower–Lowvoltage2-input multiplexer using Floating Gate MOS (FGMOS), which is subsequently used to design and simulate 4-input Multiplexer tree. This paper further investigates the performance of FGMOS based Multiplexer tree and its comparison with the conventional CMOS based multiplexer circuit. The FGMOS is a technique that offers variability in threshold voltage with significant adjustment of the bias voltage. Moreover, the current trends in VLSI demands the use of techniques that remain compatible with the decreasing feature size along with increasing density, device reliability and speed by ensuring the less power consumption, low voltage operation and reduction in the overheating, for which FGMOS is a considerable choice. Also, Low voltage circuit techniques plays a vital role in the designing of battery powered mixed signal microelectronic systems. The simulations in the proposed paper are carried out in LTSPICE using TSMC 180nm technology and 1-voltsupply. As compared to the conventional CMOS based 2-input multiplexer, FGMOS based 2-input multiplexer has 84 % lesser power consumption whereas FGMOS based 4-input multiplexer has 70 % lesser power consumption when compared to conventional CMOS based4-input multiplexer which in turn will tremendously reduce the problem of overheating in mux switching devices. It is also observed that as the order of FGMOS based multiplexer is increasing, there is an improvement in the delay, PDP and EDP.
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