Fabrication Process of MBCFET and its Characteristics

Authors

Amarah Zahra
Department of Electronics and Communication Engineering Dr B R Ambedkar National Institute of Technology Jalandhar, India Jalandhar, India
Tarun Chaudhary
Dept. of Electronics & Communication Engineering, Dr. B. R. Ambedkar National Institute of Technology, Jalandhar, India
Farhana Shahid
Department of Electronics and Communication Engineering Dr B R Ambedkar National Institute of Technology Jalandhar, India Jalandhar, India
Hritwik Todawat
Department of Electronics and Communication Engineering Dr B R Ambedkar National Institute of Technology Jalandhar, India Jalandhar, India
Vaishnawi Singh
Department of Electronics and Communication Engineering Dr B R Ambedkar National Institute of Technology Jalandhar, India Jalandhar, India
Vidhya Sagar
Department of Electronics and Communication Engineering Dr B R Ambedkar National Institute of Technology Jalandhar, India Jalandhar, India
Vineeta Sahani
Department of Electronics and Communication Engineering, Dr B R Ambedkar National Institute of Technology, Jalandhar (Punjab), India

Synopsis

This paper demonstrates the fabrication process of a novel 3-D multibridge-channel MOSFET, using the conventional CMOS process. It contains a comparative study of I-V characteristics between planer MOSFET and MBCFET. It shows how conventional MBCFET has a disadvantage of poor gate bias control and leakage characteristics and how it can be avoided by using core insulator.

WREC21
Published
September 22, 2021
Online ISSN
2582-3922