Comparative Analysis of Multiplications Technique Conventional, Booth, Array Multiplier and Vedic Arithmetic Using VHDL


Akash Kumar
Dept. of ECE, SCRIET, CCSU Campus, Meerut, India
Tarun Chaudhary
Dept. of Electronics & Communication Engineering, Dr. B. R. Ambedkar National Institute of Technology, Jalandhar, India
Vijay Kumar Ram
Dept. of ECE, SCRIET, CCSU Campus, Meerut, India


The multiplication operation is one of the often used operation in many computer and electronic devices. Low power utilization is one of the most essential attributes for meeting several challenges in many applications. In this paper different type of implementation of Booth multiplier has been studied. Multipliers has great importance in digital signal processing, so designing a high speed multiplier is the need the hour. Structures of 4X4 bits Urdhva Tiryagbhya, Nikhilam Sutra have been executed on Spartan 3 XC3S50-5-PQ-208.The determined calculation delay for 4X4 Urdhva Tiryagbhyam was 14.14 ns and force is 20.60 mw. For Nikhilam Sutra the determined computational postponement is 16.16 ns and all out force utilization is 24.60 mw.

September 22, 2021
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