Design and Simulation of Silicon Nanowire Tunnel Field Effect Transistor


Parveen Kumar
ECE Department Dr. B.R. Ambedkar National Institute of Technology Jalandhar, India
Balwinder Raj
ECE Department National Institute of Technical Teachers Training and Research Chandigarh, India


This paper analyses the different parameters of tunnel field-effect transistor (TFET) based on silicon Nanowire in vertical nature by using a Gaussian doping profile. The device has been designed using an n-channel P+-I-N+ structure for tunneling junction of TFET with gate-all-around (GAA) Nanowire structure. The gate length has been taken as 100 nm using silicon Nanowire to obtain the various parameters such as ON-current (ION), OFF-current (IOFF), current ratio, and Subthreshold slope (SS) by applying different values of work function at the gate, the radius of Nanowire and oxide thickness of the device. The simulations are performed on Silvaco TCAD which gives a better parametric analysis over conventional tunnel field-effect transistor.

September 22, 2021
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