Simulation of Counter Based DPWM for implementation on FPGA

A Digital Pulse Width Modulation technique based on the counter has been considered for analysis and simulation. It utilizes one of the many functions due to the advanced characteristics already present on the field-programmable gate array (FPGA) which is a huge advantage. Delay Locked Loop (DLL) is one of those features on the FPGA that is used. This architecture merged a counter-comparator-based synchronous block with an asynchronous block that uses the Delay Locked Loop (DLL). This action helps to achieve a better or higher resolution. The architecture proposed is to be executed on an inexpensive but lower-speed FPGA. This FPGA is given a 32 MHz clock externally that helps us to get a time resolution under 2ns. To use the DLL on FPGA, the Digital Clock Manager (DCM) block is used.